1. Field of the Invention
The present invention generally relates to avoiding read after write hazards when a write buffer is used and more specifically to reducing the latency of read after write interlocks.
2. Description of the Related Art
Current processing systems interlock reads that follow writes to the same address until the write transaction is completed, i.e. the write data is stored in memory, to prevent read after write (RAW) hazards. Therefore, the read transaction is delayed while the write transaction is pending and the latency incurred by delaying the read transaction reduces the memory transaction throughput. The latency may be even greater when one or more write transactions are cached in order to accumulate smaller write transactions to perform a block write operation.
Accordingly, what is needed in the art is a system and method for reducing the latency of read after write interlocks to improve memory transaction throughput.